To Implement Decimator and Interpolator for Multirate DSP using FPGA (Record no. 13564)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00351nam a22001217a 4500 |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Rahul Jagdale |
| 245 ## - TITLE STATEMENT | |
| Title | To Implement Decimator and Interpolator for Multirate DSP using FPGA |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | Mumbai ; |
| Year of publication | 2019 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | [60p.] |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | EXTC |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Amit Pandey : Maaz Ahmed ; Onasvi Singh ; Lakshmi Vinayakvitthal |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Project Reports |
| Withdrawn status | Lost status | Damaged status | Not for loan | Collection code | Permanent Location | Current Location | Date acquired | Accession Number | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|
| Project Reports | Don Bosco Institute of Technology Library | Don Bosco Institute of Technology Library | 13/07/2024 | PR193 | 13/07/2024 | Project Reports |