| 000 | 00351nam a22001217a 4500 | ||
|---|---|---|---|
| 100 | _aRahul Jagdale | ||
| 245 | _aTo Implement Decimator and Interpolator for Multirate DSP using FPGA | ||
| 260 |
_aMumbai ; _c2019 |
||
| 300 | _a[60p.] | ||
| 650 |
_aEXTC _97925 |
||
| 700 | _aAmit Pandey : Maaz Ahmed ; Onasvi Singh ; Lakshmi Vinayakvitthal | ||
| 942 | _cPR | ||
| 999 |
_c13564 _d13564 |
||